1. Technical Field
Various embodiments of the present invention relates to a semiconductor apparatus and related methods. In particular, certain embodiments relate to a semiconductor apparatus including a plurality of chips using chip IDs.
2. Related Art
Recently, capacities and speeds of semiconductor memories, which are used as memory devices in most electronic systems, tend to be increased. Various attempts have been made to increase the capacity of memories within their narrower area while maintaining the driving efficiency thereof.
In order to improve the degree of integration of semiconductor memories, a three-dimensional (3D) layout, in which multiple memory chips are stacked, has been adopted in place of the existing two-dimensional (2D) layout. Since the industry needs higher degree of integration and higher capacity of semiconductor memories, it is expected that demand for a structure for increasing the capacity and decreasing the size of a semiconductor chip by using a 3D layout of memory chips will increase in the art.
A TSV (through-silicon via) scheme has been used as such a 3D layout structure. The TSV scheme has been adopted as an alternative to overcome reduction of a transmission speed due to a distance to a controller on a module, narrow data bandwidth, and reduction of a transmission speed due to varying conditions in a package. In the TSV type semiconductor, paths are defined to pass through a plurality of memory chips, and electrodes are formed in the paths so that respective memory chips and a controller can communicate with each other. In a stacked semiconductor memory apparatus to which the TSV scheme is applied, wires, sub packages and package balls, which are used in an SIP type and a POP type, are not needed, and direct connections to the controller are formed through vias. Bumps are formed between paths which pass through the plurality of memory chips, to electrically connect the respective memory chips with the controller.
In a semiconductor memory apparatus including a plurality of chips which adopt the TSV scheme, different chip IDs are assigned to the plurality of chips to allow selection of desired chips. The respective chip IDs are assigned to the plurality of chips, and a system including the semiconductor memory apparatus can select an intended chip in the semiconductor memory apparatus by inputting a chip selection code through a controller to the semiconductor memory apparatus. As a method for assigning the chip IDs to the plurality of chips, a recording operation such as fuse cutting is performed for a recording element for a one-time use. However, the recording operation such as the fuse cutting is difficult to be performed in a semiconductor memory apparatus in which stacking is implemented in the TSV, and requires substantial cost and time.
Further, in the semiconductor memory apparatus using the TSV scheme, a redundancy chip should be additionally disposed in order to prevent all the chips from becoming useless in case any one of the plurality of chips is failed.